Conventionally, a cost reduction has been advanced by reducing a cell dimension in a semiconductor memory device. However, in conjunction with a reduction of a processed dimension, there is going to come to a condition that a cost by a lithography rises, and the reduction of dimension is not directly connected with the cost reduction. Even by using a double patterning which can reduce a width of drawing while using the conventional lithography device, a cost increase due to an increase of the process number comes to a bottle neck.
As a means for solving this condition, a so-called bit cost scalable memory (BiCS) has been proposed. In this method, a memory hole coming to a memory is formed in a stacked gate configuration, and an insulating film including a charge storage layer, and a semiconductor film coming to a channel are formed in an inner portion. It is possible to increase a bit number per unit area and reduce a manufacturing cost by increasing the number of stack.
In the BiCS in which a degree of integration is improved, how a charge retaining property is improved is going to be important.